1. Field of the Invention
The present invention relates to digital circuits and, more particularly to a method and circuit for recycling charge in digital circuits.
2. Background Information
For integrated circuits and, in particular, integrated circuits including digital electronic circuits, the frequency of operation and integrated circuit transistor count for such circuits continues to increase as semiconductor technology continues to advance. As a result, the power consumption of an integrated circuit also continues to increase. However, reducing the power consumption of an integrated circuit is desirable, especially for mobile or portable applications, such as laptop computers, cellular telephones and the like.
Typically, power consumption has been reduced by reducing the power supply voltage level. Reducing the power supply voltage level has been beneficial because power consumption is proportional to the square of the voltage level. However, a lower limit exists on the ability to reduce the supply voltage level due at least partially to transistor threshold voltage levels. Therefore, another technique to reduce power consumption would be desirable.
A charge recycling differential logic circuit that has been developed is one example to reduce power consumption. See, for example, "Charge Recycling Differential Logic (CRDL) for Low Power Application" by Bai-Sun Kong, Joo-Sun Choi, Seog-Jun Lee, and Kwyro Lee, appearing in IEEE Journal of Solid-State Circuits, Vol. 31, No. 9, September 1996, herein incorporated by reference. In this article, a technique is described in which digital signals are converted into differential signals and a precharge clock phase is employed to redistribute charge in the circuit. During an evaluation clock phase, a sense amplifier is employed and then generates the digital output signals. This approach reduces power consumption compared to domino logic circuit approaches. However, this approach also consumes more power than static complementary metal-oxide-semiconductor (CMOS) circuits. In particular, the interconnect loading is doubled in comparison with a static CMOS circuit because the digital signals are converted to differential pair signals. Likewise, additional gates are employed for overhead and these additional gates consume additional power.
A need, therefore, exists for a circuit or technique for reducing power consumption relative to static CMOS circuits.